Photovoltaic devices (solar cells) utilize the specific conductivity properties of semiconductors to convert the visible and near visible light energy of the sun into usable electrical energy. This conversion results from the absorption of radiant energy in the semiconductor materials which frees some valence electrons, thereby generating electron-hole pairs. The energy required to generate electron-hole pairs in a semiconductor material is referred to as the band gap energy, which in general is the minimum energy needed to excite an electron from the valence band to the conduction band.
Cadmium telluride (CdTe) has long been recognized as a promising semiconductor material for thin-film solar cells due to its near-optimum band gap of 1.44 eV and high absorption coefficient. CdTe is typically coupled with a second semiconductor material of different conductivity type such as cadmium sulfide (CdS) to produce a high-efficiency heterojunction photovoltaic cell. Small-area CdS/CdTe heterojunction solar cells with solar energy to electrical energy conversion efficiencies of more than 15% and commercial-scale modules with efficiencies of about 9% have been produced using various deposition techniques, including close-space sublimation or "CSS" (U.S. Pat. No. 5,304,499, issued Apr. 19, 1994 to Bonnet et al.), spray deposition (e.g., J. F. Jordan, Solar Cells, 23 (1988) pp. 107-113), and electrolytic deposition (e.g., B. M. Basol, Solar Cells), 23 (1988), pp. 69-88).
Thin film CdS/CdTe superstrate-type solar cells typically comprise an optically transparent substrate through which radiant energy enters the device, the intermediate layers of dissimilar semiconductor materials (e.g., CdS and CdTe), and a conductive film back contact. Generally, when the superstrate is not electrically conductive, a thin layer of transparent conductive oxide (TCO) is deposited between the substrate and the first semiconductor layer to function as a front contact current collector. However, conventional TCOs, such as tin oxide, indium oxide, and zinc oxide, have high sheet resistivities (typically about 10 ohms per square), and hence poor conductivity, at thicknesses necessary for good optical transmission. Thus, because of their high sheet resistivities, conventional TCOs are not efficient current collectors in solar cells of any appreciable size (i.e., greater than about one square centimeter), particularly in commercial-scale modules.
One way around the current collection limitation described above is to incorporate a more efficient current collection means, such as a front contact current collector grid, into the TCO layer. These current collector grids generally comprise a network of very low resistivity material that collects electrical current from the transparent conductive layer and channels the current to a central current collector. For example, U.S. Pat. Nos. 4,647,711; 4,595,790; and 4,595,791 to Basol et al. each disclose a photovoltaic device having a metallic conductive grid integrated into the TCO layer to decrease the series resistance of the device. Although supplementing the TCO layer with a metallic grid may theoretically enhance the current collecting capacity of the solar cell, because the grid material is not optically transparent, the presence of the grid can actually reduce the overall conversion efficiency of the photovoltaic device. Other disadvantages and potential problems commonly associated with the use of current collector grids include diffusion of the grid material into the semiconductor layers, short circuiting of the device, and incomplete or uneven deposition of the semiconductor layers due to the geometry of the grid.
It is desirable to create a transparent conducting film between the substrate and the first semiconductor layer that has both low electrical sheet resistance and high optical transmission. Low sheet resistance is a primary requirement of any contact on a semiconductor device to reduce the barrier to carrier flow between the semiconductor device and the external electronic circuit. High optical transmission is also very important to increase the amount of electromagnetic radiation that is absorbed by the semiconductor material, thereby optimizing the operation of the photovoltaic device by maximizing the number of photogenerated electrons available for collection. Unfortunately, it is difficult to provide both of these conditions simultaneously, low sheet resistance and high optical transmission, in the transparent conducting layer using conventional methods and TCO materials. As previously stated, conventional TCOs can have high inherent resistivity. High sheet resistance causes ohmic losses in the transparent conducting film which decreases the overall conversion efficiency of the device. To reduce the sheet resistance of these conventional TCO films, and thus potentially improve device performance, the TCO must be deposited as a relatively thick layer. However, the thicker the transparent conducting film, the lower the transmission and thus the less electromagnetic radiation that reaches the semiconductor material, thereby reducing the conversion efficiency of the solar cell.
Another disadvantage associated with conventional TCO layers in thin film solar cell devices is their generally rough surface morphology. For example, one of the most popular TCOs currently in use, tin oxide (SnO.sub.2), when deposited as a thin film by chemical vapor deposition (CVD) typically produces an average surface roughness of between about 100 and 250 .ANG.. Such high surface roughness has several significant disadvantages. First, it is well known that high-efficiency thin film CdS/CdTe solar cells require a very thin semiconductor (CdS) window layer, typically with a thickness of around 600 .ANG.. However, this high SnO.sub.2 surface roughness coupled with a thin CdS layer can significantly affect the uniformity of both the CdS layer and the resulting CdS.sub.1-x Te.sub.x intermixed layer which will be described in more detail below. If the CdS and CdS.sub.1-x Te.sub.x layers are not uniform or complete, this has the adverse effect of increasing interface defects and the density of localized TCO/CdTe junctions, thus reducing open circuit voltage and fill factor, and can ultimately cause severe degradation. Second, a high-surface roughness increases the junction area of the solar cell, which causes an increased dark current, and hence, a lower open circuit voltage and fill factor. Finally, it is desirable to create a smooth surface on the transparent conducting film so that the thickness of the semiconductor window layer can be minimized. Having a very thin window layer means more absorption of optical photons (particularly energy of short wavelength) in the active region of the semiconductor device, and thus improved photovoltaic conversion efficiency.
Another problem with conventional SnO.sub.2 films is that they can be very difficult to pattern which limits their commercial applications. It is especially important for commercial applications that the transparent conducting film be easy to pattern or etch, particularly for advanced module and display device processing. Transparent conducting films suitable for commercial use must also be easy to produce, inexpensive, durable, stable under standard processing conditions, and chemically compatible with adjacent semiconductor materials, specifically the CdS window layer.
A well-known advantage of heterojunction solar cells, such as CdS/CdTe structures, is that they can have a relatively wide band gap in the window-layer component of the cell (e.g., CdS with a bandgap of about 2.4 eV) which allows more of the electromagnetic solar radiation to pass through the front layer component and penetrate into the underlying direct band gap component where the electromagnetic solar radiation is absorbed (e.g., CdTe with a bandgap of about 1.44 eV), to create electron-hole pairs. However, the window-layer component with its wider band gap does absorb some of the electromagnetic solar radiation, especially in the shorter wavelengths below about 500 nm before it can reach the underlying absorption layer. Therefore, that shorter wavelength, e.g., blue light energy, is lost as heat instead of being usefully converted to electric current. Reducing the thickness of the window layer reduces this solar energy absorption in the window layer so that it can be absorbed near the CdS/CdTe junction, yielding increased short-circuit current (J.sub.sc) and improved overall conversion efficiency of the device. In CdS/CdTe solar cells, such reduction in the thickness of the CdS window layer allows more of the shorter wavelength or blue solar radiation to reach and be absorbed by the CdTe layer, thus improving the blue spectral response of the device.
Unfortunately, reducing the thickness of the CdS film can also cause other problems that are detrimental to the electrical quality and performance of the heterojunction device. For example, the thinner the CdS layer, the greater the probability of pinhole defects which create localized TCO/CdTe junctions that result in reduced open-circuit voltage (V.sub.oc) and fill factor (F.F.). Creation of such localized TCO/CdTe junctions can lower the V.sub.oc of a CdS/CdTe heterojunction solar cell from a range of 800-850 mV down to a range of about 300-400 mV, depending on the severity and density of the pinholes, thickness of the CdS layer and several other factors. Therefore, while thinner CdS window layers are desirable for obtaining higher solar energy conversion efficiency and high J.sub.sc, current technology is limited in how thin the CdS front or window layer can be made before the reduction of V.sub.oc and fill factor (F.F.) due to creation of pinholes as described above.
Another problem commonly associated with fabrication of thin film semiconductor devices is the formation of the back electrical contacts in a low resistance, ohmic manner to the CdTe layers. It is well known that p-CdTe is very difficult to dope to high levels. One conventional technique is to chemically etch the CdTe layer prior to deposition of the metallic-back contact to form a tellurium-rich p.sup.+ conductivity region at the exposed surface of the CdTe. Then the back contact is either deposited on the etched surface of the CdTe layer using metals such as gold or nickel, or it is formed by applying a HgTe:Cu doped graphite paste. Unfortunately, conventional chemical etching is difficult to control and the CdTe layer is polycrystalline, so excessive chemical etching can preferentially etch grain boundaries in the polycrystalline CdTe, removing Cd to leave highly conductive Te channels extending through the CdTe layer to the CdS/CdTe junction. This is detrimental by often corroding through the CdS layer and into close proximity to the TCO layer. Once the back contact is deposited, such channels can form highly conductive shunts that cause electrical short circuits between the front TCO contact and the back metal contact and reduce the V.sub.oc of the device. Therefore, while the chemical etching can enhance a desirable ohmic contact between the CdTe layer and the back contact layer, it can also have a detrimental effect on the V.sub.oc and fill factor (F.F.), thereby adversely affecting solar energy conversion efficiency of the device.
Before the chemical etching step described above, an annealing step, which typically involves heating the CdS/CdTe semiconductor heterojunction structure in a CdCl.sub.2 atmosphere, is considered by persons skilled in the art to be almost essential to produce high-efficiency CdTe devices. Such annealing provides a number of benefits, including increased grain size, grain boundary passivation, improved CdS/CdTe interface alloying, and reduced lattice mismatch between the CdS and CdTe layers. Unfortunately, CdCl.sub.2 heat treatment, like chemical etching, is difficult to control, and over-processing can significantly reduce both device performance and product yield. Moreover, it is believed that grain growth, although a generally desirable result of CdCl.sub.2 heat treatment, can induce stress at the TCO/CdS interface, causing blistering or peeling of the semiconductor layers.
Most efforts to solve these problems with constructing high-efficiency CdS/CdTe semiconductor heterojunction devices have been directed to refining layer compositions, thicknesses, and processing control parameters to optimize a balance between the beneficial and adverse effects described above. However, U.S. Pat. No. 5,261,968 issued to Jordan addresses the problem of pinhole shunts between the TCO and CdTe layers through the CdS layer by interposing a low conductivity tin oxide layer between the high conductivity TCO layer and the CdS layer. In that patent, the TCO is a high-conductivity tin oxide, while the interposed low conductivity tin oxide layer has its carrier concentration adjusted by a cadmium, zinc, or other metal dopant. However, solutions to the problem of electrical short circuits through grain boundary shunts from chemical etching of the CdTe layer and to the problems of blistering and peeling between the TCO/CdS layers and other degradation from overprocessing in the annealing step have remained elusive.
It would be desirable to develop improved processes for fabricating such semiconductor devices, especially if more steps could be conducted at ambient temperature to reduce the thermal budget for the process.
U.S. Pat. No. 5,393,675 to Compaan discloses a thin film photovoltaic cell having CdS and CdTe layers deposited sequentially onto a conductive tin oxide layer by RF magnetron sputtering. However, the patent does not disclose a CdTe device including layers of cadmium stannate and zinc stannate, nor a method of depositing layers of a transparent conducting oxide or CdS at ambient temperature.
U.S. Pat. No. 4,231,808 to Tabei et al. discloses methods for manufacturing CdTe thin film solar cells containing a CdTe thin layer involving a shallow p-n homogeneous junction. An n-CdTe film was deposited by RF sputtering at 300.degree. C., then heat treated to form a shallow p-n junction. This patent does not disclose or suggest a heterojunction CdS/CdTe thin film device such as claimed herein, nor a method for depositing the first two or three layers of such a cell by RF sputtering at ambient temperature.
U.S. Pat. No. 4,445,965 to Milnes discloses a method for making thin semiconductor films for use in solar cells, using single or near-single crystal material of CdTe or related semiconductors. There is no suggestion of a process for fabrication of polycrystalline CdS/CdTe thin-film solar cells.
U.S. Pat. No. 4,596,645 to Stirm discloses a reactive sputtering technique for making a high conductivity, n-doped semiconductor film for heterojunction devices.
U.S. Pat. No. 5,180,476 to Ishibashi et al. discloses methods for making transparent conductive films by sputter deposition at temperatures over 200.degree. C., using materials based upon oxides of indium, tin, zinc, cadmium/tin or cadmium/indium. There is no suggestion of sputter deposition of materials such as those used in the present invention at ambient temperatures.
U.S. Pat. No.4,709,466 to McCandless et al. discloses a post-deposition annealing process for fabricating thin-film photovoltaic devices in which the devices' fill factor is increased from 46 to 54 percent.
U.S. Pat. No. 5,714,391 to Omura et al. discloses a method for manufacturing a compound semiconductor thin film for a photoelectric or solar cell device. The thin film is derived from a metal sulfide produced by thermal decomposition of a sulfur-containing metal organic compound. CdS/CdTe cells are said to be improved by employing such a CdS layer deposited at a substrate temperature of 450.degree. C. There is no suggestion of depositing such layers at ambient temperatures.
Commercial scale photovoltaic modules having efficiencies of 6-9 percent have been prepared by several CdTe deposition techniques, including modified close-space sublimination (CSS), chemical spray deposition and electrodeposition. However, the first three layers (including a tin oxide TCO layer, an insulating tin oxide buffer layer and a CdS window layer) were deposited conventionally at high temperatures (e.g., chemical vapor deposition, CSS and spray techniques) or in liquid solution (i.e., electro deposition techniques) by at least three manufacturers, as outlined in Table 1. Such high temperature deposition steps or the treatment of large amounts of liquid wastes will increase manufacturing costs.
In addition, the use of different deposition techniques for applying these three layers will also increase the investment in manufacturing equipment. In the present process, as outlined in Table 1, these first three steps can be carried out by radio frequency (RF) sputtering at room or ambient temperature.
TABLE 1 ______________________________________ Manu- CdS Window facturer TCO layer Buffer layer Layer ______________________________________ No. 1 CVD-SnO.sub.2 Sputtered I--SnO.sub.2 CSS-CdS 550.degree.-600.degree. C. (for R & D) 550.degree.-600.degree. C. No. 2 CVD-SnO.sub.2 Spray-Cd-doped Spray-CdS 550.degree.-600.degree. C. SnO.sub.2 500.degree.-550.degree. C. 500-550.degree. C. No. 3 CVD-SnO.sub.2 NA Electro-deposition- 550.degree.-600.degree. C. CdS .about.100.degree. C. Present work RF sputtered RF sputtered RF sputtered Cd.sub.2 SnO.sub.4, RT Zn.sub.2 SnO.sub.4, RT CdS, RT ______________________________________
Our prior application U.S. Ser. No. 08/746,798 now U.S. Pat. No. 5,922,142 discloses methods of fabricating similar devices, comprising steps of RF sputter coating amorphous cadmium stannate onto a substrate, coating a second substrate with CdS, contacting the layers of cadmium stannate and CdS, then heating the substrates and layers of material to crystallize the cadmium stannate layer, cooling the substrates, and separating the two substrates. While producing a substrate with a layer of polycrystalline cadmium stannate providing improved optical and electrical properties, this method is very cumbersome on a commercial scale.
Our prior application Ser. No. 09/149,430 discloses methods of preparing similar devices including a buffer layer of zinc stannate interposed between the TCO front contact layer (which can be cadmium stannate) and the CdS front window layer of a CdS/CdTe heterojunction device. The method includes steps of applying a TCO layer to a transparent substrate, depositing a zinc stannate layer onto this TCO layer, then depositing as thin films two or more layers of semiconductor materials to form a p/n or p/i/n junction onto the layer of zinc stannate, and finally depositing an electrically conductive film onto the thin film layers of semiconductor materials to form a rear contact.